Senior High-Speed Front End & IP Physical Designer
Job Description
Senior Front End Integration & Physical Design Engineer
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Senior Front End Integration & Physical Design Engineer
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This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$103,200.00/yr - $154,800.00/yr
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
The Role
In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The NBIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.
The Person
As a Design Engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
KEY RESPONSIBILITIES:
We are currently looking for a Senior Design Engineer will focus on all physical implementation aspects of next generation IPs. This team deals with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer. This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.
The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.
PREFERRED EXPERIENCE:
- Strong industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.
- CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python
- Bachelors or Masters degree in computer engineering/ Electrical Engineering
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability, or any other characteristic protected by law. EOE/MFDV
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Seniority level
Seniority level
Mid-Senior level
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Full-time
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Semiconductor Manufacturing
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